`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:22:47 03/17/2022 
// Design Name: 
// Module Name:    pc_reg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "define.v"
module pc_reg(
	input wire clk,
	input wire rst,
	input wire branch_flag_i,
	input wire[`RegBus] branch_target_address_i,

	output reg[`InstAddrBus] pc,
	output reg ce
    );
	 /*
	 initial begin
		ce = 0;
		pc = 32'h0;
	 end*/
	 
	 
	 always @(posedge clk)begin
		if(rst == `RstEnable) begin
			ce<=`ChipDisable;
		end
		else begin
			ce<=`ChipEnable;
		end
	 end
	 
	 always @(posedge clk)begin
		if(ce ==`ChipDisable)begin
			pc<=32'h0;
		end else if(branch_flag_i == `Branch)begin
			pc <= branch_target_address_i;
		end else begin
			pc<=pc+4'h4;
		end
	 end


endmodule
